TCAD Investigation of Novel CMOS Devices for Sub 14 nm Technology

Abstract

In consensus with the Moore's law, size of the transistor is scaled down to improve transistor performance, and thereby, cost per function. However, with the reduced size the variability in transistor is significantly increased which affects the yield of chips. Threshold voltage is one of the important parameter which gets affected by process variability as an example; increasing Vth for a 6-transisitor Static RAM circuit limits the operating voltage of the circuit. Process variability restricts the scaling process and causes performance degradation. There is a strong need for qualitative and quantitative measurement of different factors of variability in order to decrease the yield loss. Different variability reduction technique like use of low doped devices, advanced lithography techniques should be adopted to reduce it or new device structure could be proposed which resist or are less affected by variability. In this work three type of process variation have been studied: Line Edge Roughness, Random Dopant Fluctuation, and Metal Gate Granularity and analyzed for their the effect on Nanowire and FinFET. Nanowire could be seen as a replacement of FinFET in future technologies due to its large gate control, decreased dimensions and better control on device variability. The comparison of FinFET and Nanowire is performed with Inversion mode, Accumulation and Junctionless mode doping profiles. The results establish that inversion mode and accumulation mode devices are better option for the designer. Hence, a fair choice is offered to a designer to select a suitable doping profile for the structure which results in less variability and better scalability of the device. In the next phase of work a novel inverter design has been proposed which is based on multi SOI wafer. It is an inverter embedded into a single fin consisting of two regions: one region acts as a p-type FET and other acts as n-type FET separated by an inserted oxide. This multi-layer technology enables to have a reduced chip area with lesser parasitic capacitance leading to faster circuits with more functionality.