Design and Analysis of Low Power Ultra Windeband Low Noise Amplifier

Abstract

The objective of this thesis is to design a low power Low Noise Amplifier (LNA) for Ultra Wideband (3.1 - 10.6 GHz) applications using standard 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. In order to reduce power consumption, LNA is operated in sub-threshold region. Parasitic capacitances of the MOSFET are utilized in design for achieving wideband input impedance matching. Forward Body Bias technique is used to reduce the threshold voltage of the MOSFET. This helps to reduce the requirement of high supply voltage. Inductive peaking is used to achieve good gain at high frequencies. To reduce power consumption, Current Reuse technique is used. The low noise design strategy is mainly based on the analysis of high frequency CMOS operation. The LNA exhibits power gain (S21) of 14 dB, an Input Reflection Coefficient (S11) of less than -6 dB, a noise figure of 1.8 dB while having a power consumption of 7.2 mW for a voltage supply of 1.2 V. This LNA design achieves output reflection coefficient (S22) value lower than -6 dB. The UWB LNA is simulated in Advanced Design System (ADS 2011.05). The PDK used in the simulation is from United Microelectronics Corporation (UMC). The technology used for designing this LNA is 130 nm CMOS technology.